3.5 Segmentation and Paging

1. Physical and Virtual Addresses

A physical address identifies a location in physical memory.

A virtual address belongs to a process’s virtual address space. The MMU translates it using page tables configured by the kernel.

The usable virtual-address width is determined by the architecture and implementation; it is not simply min(RAM + disk, 2^CPU-bits).

2. Paging

Paging divides virtual memory and physical memory into fixed-size units:

• virtual pages;
• physical page frames.

A page table records mappings and permissions.

Benefits include:

• no requirement for a process to occupy one contiguous physical region;
• simple fixed-size allocation units;
• demand paging and copy-on-write;
• page-granular protection.

Costs include page-table memory, translation overhead, and internal fragmentation within the last page of an allocation.

3. Segmentation

Segmentation divides an address space into variable-size logical regions described by a base and limit.

Historically, segmentation represented logical units such as code, data, and stacks. Variable-size allocation can suffer external fragmentation.

4. Segmentation + Paging

Some architectures and textbooks combine segmentation with paging: a segment selects a logical region, then paging maps pages within that region.

This is not a universal model for modern virtual memory. Modern 64-bit operating systems commonly use paging as the primary memory-translation mechanism; segmentation may be minimized, compatibility-oriented, or used for specialized architectural purposes.

5. TLB

Because page-table walks are expensive, CPUs cache translations in the TLB. Context switches, address-space identifiers, huge pages, and mapping changes all interact with TLB behavior and therefore affect real memory-performance costs.